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Disambiguation of "Gupta, Hari Shanker"

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Analysis of an Interior Penalty Method for Fourth Order Problems on Polygonal Domains.

, , and . J. Sci. Comput., 54 (1): 177-199 (2013)

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Shanker Dave

Sreejesh Shanker

Hari Paudel

Hari Petsos

Jürg Hari

 

Other publications of authors with the same name

A 105-525MHz Integer-N Phase-Locked Loop in Indigenous SCL 180nm CMOS., , , and . VLSID, page 348-352. IEEE, (2023)Low Power Configurable Readout Integrated Circuit for Infrared Detector., , , , and . VLSID, page 198-203. IEEE Computer Society, (2018)Large Dynamic Range Readout Integrated Circuit for Infrared Detectors., , , , , and . VLSID, page 311-316. IEEE, (2019)A Mismatch Resilient 16-Bit 20 MS/s Pipelined ADC., , , , , and . VLSID, page 305-310. IEEE, (2019)Novel design of a silicon photodetector and its integration in a 4×4 CMOS pixel array., , , and . ISQED, page 462-467. IEEE, (2016)A fully discrete C0 interior penalty Galerkin approximation of the extended Fisher-Kolmogorov equation., and . J. Comput. Appl. Math., (2013)Mismatch Resilient 3.5-Bit MDAC with MCS-CFCS., , and . ISVLSI, page 175-180. IEEE Computer Society, (2018)Bipolar voltage level shifter., , , , , , , and . VDAT, page 1-5. IEEE Computer Society, (2015)Sub-nanosecond Delay High Voltage Level Shifter in 0.18μm HV-CMOS Technology for Cryo-Cooler Electronics., , , and . APCCAS, page 197-201. IEEE, (2023)Analysis of an Interior Penalty Method for Fourth Order Problems on Polygonal Domains., , and . J. Sci. Comput., 54 (1): 177-199 (2013)