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A 105-525MHz Integer-N Phase-Locked Loop in Indigenous SCL 180nm CMOS., , , and . VLSID, page 348-352. IEEE, (2023)Large Dynamic Range Readout Integrated Circuit for Infrared Detectors., , , , , and . VLSID, page 311-316. IEEE, (2019)Low Power Configurable Readout Integrated Circuit for Infrared Detector., , , , and . VLSID, page 198-203. IEEE Computer Society, (2018)A Mismatch Resilient 16-Bit 20 MS/s Pipelined ADC., , , , , and . VLSID, page 305-310. IEEE, (2019)Analysis of an Interior Penalty Method for Fourth Order Problems on Polygonal Domains., , and . J. Sci. Comput., 54 (1): 177-199 (2013)Implementation of high performance Readout Integrated Circuit., , , , , , , , and . MWSCAS, page 402-405. IEEE, (2014)A 64b/66b Line Encoding for High Speed Serializers., , , and . VLSID, page 303-308. IEEE Computer Society, (2017)A Programmable and Adaptive Dead-Time Controller for Low-Offset Output Generation for Cryo-Cooler Drive Applications., , , and . ISCAS, page 1-5. IEEE, (2024)Novel design of a silicon photodetector and its integration in a 4×4 CMOS pixel array., , , and . ISQED, page 462-467. IEEE, (2016)Mismatch Resilient 3.5-Bit MDAC with MCS-CFCS., , and . ISVLSI, page 175-180. IEEE Computer Society, (2018)