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Disambiguation of "Sathe, Visvesh S."

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Resonant-Clock Latch-Based Design.

, , and . IEEE J. Solid State Circuits, 43 (4): 864-873 (2008)

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Madan Sathe

Nita Sathe-Meis

Saket Sathe

Richard Satherley

S Danischewski

 

Other publications of authors with the same name

A GHz-class charge recovery logic., , and . ISLPED, page 91-94. ACM, (2005)Energy-Efficient GHz-Class Charge-Recovery Logic., , and . IEEE J. Solid State Circuits, 42 (1): 38-47 (2007)Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control., , , , , , and . IEEE J. Solid State Circuits, 57 (1): 90-102 (2022)Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains., , , , and . IEEE J. Solid State Circuits, 58 (1): 68-77 (2023)A 1.1ghz charge-recovery logic., , and . ISSCC, page 1540-1549. IEEE, (2006)Boost Logic: A High Speed Energy Recovery Circuit Family., , and . ISVLSI, page 22-27. IEEE Computer Society, (2005)Energy efficient SoC design., and . CICC, page 1. IEEE, (2013)Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic., , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (6): 977-988 (2012)Architecture Considerations for Stochastic Computing Accelerators., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (11): 2277-2289 (2018)An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS., , , , , and . VLSI Circuits, page 1-2. IEEE, (2018)