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Low-power HEVC binarizer architecture for the CABAC block targeting UHD video processing.

, , , , and . SBCCI, page 30-35. ACM, (2017)

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AV1 Residual Syntax Elements Assessment and Efficient VLSI Architecture., , , and . SBCCI, page 1-6. IEEE, (2023)Power-Saving 8K Real-Time AV1 Arithmetic Encoder Architecture., , and . IEEE Des. Test, 39 (6): 128-137 (2022)High-Throughput Binary Arithmetic Encoder using Multiple-Bypass Bins Processing for HEVC CABAC., , , and . ISCAS, page 1-5. IEEE, (2018)Area and Power Efficient 8K Real-Time Design for AV1 Arithmetic Decoding., , , and . PCS, page 7-11. IEEE, (2022)Low-power HEVC binarizer architecture for the CABAC block targeting UHD video processing., , , , and . SBCCI, page 30-35. ACM, (2017)Novel multiple bypass bins scheme for low-power UHD video processing HEVC binary arithmetic encoder architecture., , , and . SBCCI, page 47-52. ACM, (2017)A high throughput CAVLC hardware architecture with parallel coefficients processing for HDTV H.264/AVC enconding., , , , and . ICECS, page 587-590. IEEE, (2010)Residual Syntax Elements Analysis and Design Targeting High-Throughput HEVC CABAC., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 67-I (2): 475-488 (2020)Power-Throughput Trade-off Analysis for a Novel Multi-Boolean AV1 Arithmetic Encoder Design., , and . PCS, page 25-29. IEEE, (2022)Energy-Throughput Configurable Design for Video Processing Binary Arithmetic Encoder., , , and . IEEE Trans. Circuits Syst. Video Technol., 31 (3): 1163-1177 (2021)