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1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times., , , , , , , , and . VLSIC, page 46-47. IEEE, (2012)Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition., , , , , , , , , and 10 other author(s). IEEE J. Solid State Circuits, 56 (4): 1116-1128 (2021)A 90nm 12ns 32Mb 2T1MTJ MRAM., , , , , , , , , and 10 other author(s). ISSCC, page 462-463. IEEE, (2009)High-speed simulator including accurate MTJ models for spintronics integrated circuit design., , , , , , , , , and 1 other author(s). ISCAS, page 1971-1974. IEEE, (2012)Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure., , , , , , , , , and 1 other author(s). VLSIC, page 172-. IEEE, (2015)Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications., , , , , , , , , and 1 other author(s). IEICE Electron. Express, 10 (23): 20130772 (2013)A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 54 (11): 2991-3004 (2019)10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications., , , , , , , , , and 4 other author(s). ISSCC, page 184-185. IEEE, (2014)Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage., , , , , , , , , and 10 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)MRAM Cell Technology for Over 500-MHz SoC., , , , , , , and . IEEE J. Solid State Circuits, 42 (4): 830-838 (2007)