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Disambiguation of "Kastensmidt, Fernanda Lima"

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High-speed Hardware Accelerator for Trace Decoding in Real-Time Program Monitoring.

, , and . LASCAS, page 1-4. IEEE, (2021)

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Fernanda Schneider

Fernanda Rodriguez

Antonio Lima

Silvio Romero Frej Fonseca Lima

Irmtraut Liman-Bolley

 

Other publications of authors with the same name

Improving approximate-TMR using multi-objective optimization genetic algorithm., , , , , , and . LATS, page 1-6. IEEE, (2018)Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs., , , , and . ARC, volume 10216 of Lecture Notes in Computer Science, page 202-213. (2017)Applying lockstep in dual-core ARM Cortex-A9 to mitigate radiation-induced soft errors., , and . LASCAS, page 1-4. IEEE, (2017)Comparative Analysis of Inference Errors in a Neural Network Implemented in SRAM-Based FPGA Induced by Neutron Irradiation and Fault Injection Methods., , , , and . SBCCI, page 1-6. IEEE, (2018)Combining fault tolerance and serialization effort to improve yield in 3D Networks-on-Chip., , , , , , , , and . ICECS, page 125-128. IEEE, (2013)Impact of different transistor arrangements on gate variability., , , , , and . Microelectron. Reliab., (2018)Exploring the inherent fault tolerance of successive approximation algorithms under laser fault injection., , , and . LATS, page 1-6. IEEE, (2018)On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs, , , and . CoRR, (2007)A broad strategy to detect crosstalk faults in network-on-chip interconnects., , , , and . VLSI-SoC, page 298-303. IEEE, (2010)Failure Mechanism and Sampling Frequency Dependency on TID Response of SAR ADCs., , , , , , , , , and 1 other author(s). J. Electron. Test., 37 (3): 329-343 (2021)