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Disambiguation of "Nagaraj, Krishnaswamy"

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A 1.1mW, 63.7dB-SNDR, 10MHz-BW hybrid voltage -time domain ADC.

, , and . MWSCAS, page 1053-1056. IEEE, (2014)

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Madhu Nagaraj

Arvind Krishnaswamy

Nagarjuna Nagaraj

Nuggehalli Krishnaswamy

Krishnaswamy Kadambi

 

Other publications of authors with the same name

Widely programmable high-frequency continuous-time filters in digital CMOS technology., , and . IEEE J. Solid State Circuits, 35 (4): 503-511 (2000)A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process., , , , , , and . IEEE J. Solid State Circuits, 35 (12): 1760-1768 (2000)An Embedded 65 nm CMOS Remote Temperature Sensor With Digital Beta Correction and Series Resistance Cancellation Achieving an Inaccuracy of 0.4°C (3σ) From - 40°C to 130°C., , , , , , and . IEEE J. Solid State Circuits, 50 (9): 2127-2137 (2015)Message from the Outgoing Editor-in-Chief.. IEEE J. Solid State Circuits, 42 (8): 1631 (2007)An oxide electrothermal filter in standard CMOS., , , , , and . IEEE SENSORS, page 1-3. IEEE, (2016)A Two-Stage ADC Architecture With VCO-Based Second Stage., , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (11): 734-738 (2011)Corrections to Ärea-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference"., , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (8): 639 (2014)Modeling of accumulation MOS capacitors for analog design in digital VLSI processes., , and . ISCAS (6), page 202-205. IEEE, (1999)Digital Built-in Self-Test for Phased Locked Loops to Enable Fault Detection., , , , , , and . ETS, page 1-6. IEEE, (2019)New Associate Editors.. IEEE J. Solid State Circuits, 42 (7): 1451-1452 (2007)