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A Discrete-Time Input Delta Sigma ADC Architecture Using a Dual-VCO-Based Integrator., , и . IEEE Trans. Circuits Syst. II Express Briefs, 57-II (11): 848-852 (2010)A Two-Stage ADC Architecture With VCO-Based Second Stage., , и . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (11): 734-738 (2011)Harmonic Rejection Mixing Techniques Using Clock-Gating., и . IEEE J. Solid State Circuits, 48 (8): 1862-1874 (2013)A CMOS bandgap reference without resistors., , , и . IEEE J. Solid State Circuits, 37 (1): 81-83 (2002)A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process., , , , , , и . IEEE J. Solid State Circuits, 35 (12): 1760-1768 (2000)A Unity-Gain Buffer with Reduced Offset and Gain Error., , и . CICC, стр. 825-828. IEEE, (2006)Operational current to frequency converter., , , , и . MWSCAS, стр. 900-903. IEEE, (2013)A Non-uniform Sampling Technique for A/D Conversion., , и . ISCAS, стр. 1220-1223. IEEE, (1993)An uncalibrated 2MHz, 6mW, 63.5dB SNDR discrete-time input VCO-based ΔΣ ADC., , и . CICC, стр. 1-4. IEEE, (2012)A Single-Step Subranging Relaxation Oscillator-Based Open-Loop Sigma-Delta ADC., , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (3): 993-1005 (марта 2023)