From post

A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction.

, , и . ACM Trans. Design Autom. Electr. Syst., 13 (2): 34:1-34:15 (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation., , , и . VLSI Design, 15 (3): 587-594 (2002)Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (1): 84-95 (2008)Minimum replication min-cut partitioning., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (10): 1221-1227 (1997)A GPU-Accelerated Framework for Path-Based Timing Analysis., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (11): 4219-4232 (ноября 2023)Network-flow-based multiway partitioning with area and pin constraints., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (1): 50-59 (1998)Slicing floorplans with range constraint., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (2): 272-278 (2000)Simultaneous power supply planning and noise avoidance in floorplan design., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (4): 578-587 (2005)On over-the-cell channel routing with cell orientations consideration., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (6): 766-772 (1995)A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem IC layout., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (1): 141-147 (2004)An ECO routing algorithm for eliminating coupling-capacitance violations., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (9): 1754-1762 (2006)