( en | de | ru )

 

Disambiguation of "Hunter, Hillery C."

Author of the publication

copydeleteadd this publication to your clipboard
Hardware-compiler co-design for adjustable data power savings.

, , , and . Microprocess. Microsystems, 33 (4): 244-253 (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Julia Hunter

Hunter Rouse

Charles Hunter

Regina Hunter

Aleksandra Hunter

 

Other publications of authors with the same name

An innovative low-power high-performance programmable signal processor for digital communications., , , , , , , , , and 6 other author(s). IBM J. Res. Dev., 47 (2-3): 299-326 (2003)PANEL: Open panel and discussion on tackling complexity, reproducibility and tech transfer challenges in a rapidly evolving AI/ML/systems research., , , , , and . ReQuEST@ASPLOS, page 7. ACM, (2018)Guest Editorial Computing in Emerging Technologies (Second Issue)., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (1): 1-4 (2015)Code coverage and input variability: effects on architecture and compiler research., and . CASES, page 79-87. ACM, (2002)A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 43 (1): 86-95 (2008)Hardware-compiler co-design for adjustable data power savings., , , and . Microprocess. Microsystems, 33 (4): 244-253 (2009)Enhancing loop buffering of media and telecommunications applications using low-overhead predication., , and . MICRO, page 262-273. ACM/IEEE Computer Society, (2001)Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 4635-4644 (2020)A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier., , , , , , , , , and 7 other author(s). ISSCC, page 486-617. IEEE, (2007)BlueConnect: Decomposing all-reduce for deep learning on heterogeneous network hierarchy., , , , and . IBM J. Res. Dev., 63 (6): 1:1-1:11 (2019)