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Hardware-compiler co-design for adjustable data power savings.

, , , and . Microprocess. Microsystems, 33 (4): 244-253 (2009)

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Bottom-Up and Top-Down Context-Sensitive Summary-Based Pointer Analysis., , and . SAS, volume 3148 of Lecture Notes in Computer Science, page 165-180. Springer, (2004)Hardware-compiler co-design for adjustable data power savings., , , and . Microprocess. Microsystems, 33 (4): 244-253 (2009)An Architectural Framework for Runtime Optimization., , , , , , and . IEEE Trans. Computers, 50 (6): 567-589 (2001)Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining., , , , , and . IEEE Trans. Computers, 55 (1): 18-33 (2006)Importance of heap specialization in pointer analysis., , and . PASTE, page 43-48. ACM, (2004)Vacuum packing: extracting hardware-detected program phases for post-link optimization., , , and . MICRO, page 233-244. ACM/IEEE Computer Society, (2002)A hardware mechanism for dynamic extraction and relayout of program hot spots., , , , and . ISCA, page 59-70. IEEE Computer Society, (2000)Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining., , , , , and . IEEE Trans. Computers, 55 (1): 18-33 (2006)Code Reordering and Speculation Support for Dynamic Optimization System., , , and . IEEE PACT, page 163-174. IEEE Computer Society, (2001)Field-testing IMPACT EPIC research results in Itanium 2., , , , , and . ISCA, page 26-39. IEEE Computer Society, (2004)