Author of the publication

Multi-core platform for an efficient H.264 and VC-1 video decoding based on macroblock row-level parallelism.

, , and . IET Circuits Devices Syst., 4 (2): 147-158 (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Multi-core platform for an efficient H.264 and VC-1 video decoding based on macroblock row-level parallelism., , and . IET Circuits Devices Syst., 4 (2): 147-158 (2010)An efficient motion estimation hardware architecture using Modified Reference Data Access(MRDAS) skip algorithm for high Efficiency Video Coding(HEVC) encoder., , , , and . ICCE-Berlin, page 85-89. IEEE, (2016)An efficient architecture of DCTQ module in MPEG-4 video codec., , , , , , and . ISCAS (1), page 777-780. IEEE, (2002)A 100MHz ASIP (application specific instruction processor) for CAVLC of H.264/AVC decoder., , , , and . ISCAS, page 3462-3465. IEEE, (2008)Selective clock gating by using wasting toggle rate., , , and . EIT, page 399-404. IEEE, (2009)Fast decision of CU partitioning based on SAO parameter, motion and PU/TU split information for HEVC., , and . PCS, page 113-116. IEEE, (2013)Image compression based on MR-CNN (Modified Region Convolutional Neural Network)., , , , , , and . ISOCC, page 292-293. IEEE, (2017)A 166.7 Mhz 1920×1080 60fps H.264/SVC video decoder., , and . ISOCC, page 278-281. IEEE, (2011)New Lookup Tables and Searching Algorithms for Fast H.264/AVC CAVLC Decoding., , and . IEEE Trans. Circuits Syst. Video Techn., 20 (7): 1007-1017 (2010)A hybrid embedded compression codec engine for ultra HD video application., , and . VLSI-SoC, page 292-296. IEEE, (2015)