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The future of system-level design: can we find the right solutions to the right problems at the right time?

, , , , , и . CODES+ISSS, стр. 231. ACM, (2003)

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Antoine Bergamaschi

Sidnei Bergamaschi

Josef Bergamaschi

Peter Bergamaschi

Reinaldo Espinosa

 

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Redesign using state splitting., и . EURO-DAC, стр. 157-161. IEEE Computer Society, (1990)High-level synthesis in an industrial environment., , , , , , и . IBM J. Res. Dev., 39 (1-2): 131-148 (1995)Observable Time Windows: Verifying High-Level Synthesis Results., и . IEEE Des. Test Comput., 14 (2): 40-50 (1997)The State of ESL Design Roundtable., , , , , и . IEEE Des. Test Comput., 25 (6): 510-519 (2008)State-based power analysis for systems-on-chip., и . DAC, стр. 638-641. ACM, (2003)Automatic synthesis and technology mapping of combinational logic.. ICCAD, стр. 466-469. IEEE Computer Society, (1988)Heterogeneous behavioral hierarchy for system level designs., , и . DATE, стр. 565-570. European Design and Automation Association, Leuven, Belgium, (2006)Synthesis of Arrays and Records., , , , и . ICCD, стр. 614-619. IEEE Computer Society, (1999)Bridging the domains of high-level and logic synthesis.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (5): 582-596 (2002)Introductions to special issue on ESWEEK 2011., , , , , , и . Des. Autom. Embed. Syst., 17 (2): 215-219 (2013)