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An efficient path based equivalence checking for Petri net based models of programs.

, , и . ISEC, стр. 70-79. ACM, (2016)

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Dipankar Mandal

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Diagnosability of delay-deadline failures in fair real time discrete event models., , и . Int. J. Syst. Sci., 41 (7): 763-782 (2010)Poster: An Efficient Equivalence Checking Method for Petri Net Based Models of Programs., , и . ICSE (2), стр. 827-828. IEEE Computer Society, (2015)ISBN 978-1-4799-1934-5 (Vol. I + II ???).On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models., , , , , и . Asian Test Symposium, стр. 88-93. IEEE Computer Society, (2005)Verification of Scheduling in High-level Synthesis., , , , и . ISVLSI, стр. 141-146. IEEE Computer Society, (2006)Validating SPARK: High Level Synthesis Compiler., , и . ISVLSI, стр. 195-198. IEEE Computer Society, (2015)A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques., , , и . ISED, стр. 67-71. IEEE, (2012)SamaTulyataOne: A Path Based Equivalence Checker., , и . ISEC, стр. 21:1-21:5. ACM, (2019)Model checking on state transition diagram., , и . ASP-DAC, стр. 412-417. IEEE Computer Society, (2004)A translation validation framework for symbolic value propagation based equivalence checking of FSMDAs., , и . SCAM, стр. 247-252. IEEE Computer Society, (2015)Register Sharing Verification During Data-Path Synthesis., , , и . ICCTA, стр. 135-140. IEEE Computer Society, (2007)