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Disambiguation of "Zanuso, Marco"

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Quantization Effects in All-Digital Phase-Locked Loops.

, , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (12): 1120-1124 (2007)

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Monika Marcotty

Johannes Marcour

Hans-Ernst Marcolin

Carlos Javier Marcos Navas

Massimiliano Marcon

 

Other publications of authors with the same name

An all-digital architecture for low-jitter regulated delay lines., , , , and . ICECS, page 603-606. IEEE, (2009)Multipath adaptive cancellation of divider non-linearity in fractional-N PLLs., , , and . ISCAS, page 418-421. IEEE, (2011)Quantization Effects in All-Digital Phase-Locked Loops., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (12): 1120-1124 (2007)A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power., , , , , and . ISSCC, page 88-90. IEEE, (2011)A 2.9-4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power., , , , , and . IEEE J. Solid State Circuits, 46 (12): 2745-2758 (2011)Noise Analysis and Minimization in Bang-Bang Digital PLLs., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (11): 835-839 (2009)A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation., , , and . IEEE J. Solid State Circuits, 46 (3): 627-638 (2011)Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (3): 548-555 (2010)Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (4): 200-204 (2011)Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band., , , and . ISSCC, page 50-51. IEEE, (2010)