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Disambiguation of "Agarwal, Amit"

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34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms.

, , , , , , , , , and . ESSCIRC, page 90-93. IEEE, (2018)

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Amit Agarwal

Regina Amith-Borchart

Menachem Amitai

Samuel Amiteye

Menachem Amitai

 

Other publications of authors with the same name

Leakage Power Analysis and Reduction for Nanoscale Circuits., , , , and . IEEE Micro, 26 (2): 68-80 (2006)Rectilinear workspace partitioning for parallel coverage using multiple unmanned aerial vehicles., , , and . Adv. Robotics, 21 (1): 105-120 (2007)Co- Location Resistant Virtual Machine Placement in Cloud Data Centers., and . ICPADS, page 61-68. IEEE, (2018)Layer Hall effect in a 2D topological axion antiferromagnet, , , , , , , , , and 26 other author(s). Nature, 595 (7868): 521--525 (Jul 21, 2021)A graph theoretic approach for modelling tiger corridor network in Central India-Eastern Ghats landscape complex, India., , , , , , and . Ecol. Informatics, (2019)A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 56 (4): 1082-1092 (2021)Process variation in embedded memories: failure analysis and variation aware architecture., , , and . IEEE J. Solid State Circuits, 40 (9): 1804-1814 (2005)An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 54 (4): 1074-1085 (2019)53 Gbps Native GF(2 4) 2 Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors., , , , , , , , and . IEEE J. Solid State Circuits, 46 (4): 767-776 (2011)2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors., , , , , , , , and . IEEE J. Solid State Circuits, 47 (11): 2807-2821 (2012)