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FusedGCN: A Systolic Three-Matrix Multiplication Architecture for Graph Convolutional Networks.

, , , and . ASAP, page 93-97. IEEE, (2022)

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Practical High-Throughput Crossbar Scheduling., and . IEEE Micro, 29 (4): 22-35 (2009)A management scheme for improving transportation efficiency and contributing to the enhancement of the social fabric., , , and . Telematics Informatics, 26 (4): 375-390 (2009)Switch folding: network-on-chip routers with time-multiplexed output ports., , , and . DATE, page 344-349. EDA Consortium San Jose, CA, USA / ACM DL, (2013)DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity., , , and . CoRR, (2024)ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining., , , , and . CoRR, (2022)Networks-on-Chip With Double-Data-Rate Links., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (12): 3103-3114 (2017)Memristive Oscillatory Circuits for Resolution of NP-Complete Logic Puzzles: Sudoku Case., , , , , , and . ISCAS, page 1-5. IEEE, (2020)Dynamic Adjustment of Test-Sequence Duration for Increasing the Functional Coverage., , , and . IVSW, page 61-66. IEEE, (2019)Backlog-Aware Crossbar Schedulers: A New Algorithm and its Efficient Hardware Implementation., and . Hot Interconnects, page 67-74. IEEE Computer Society, (2008)2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD)., , , , , , and . DFT, page 1-4. IEEE, (2020)