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DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity.

, , , and . IEEE Comput. Archit. Lett., 23 (1): 17-20 (January 2024)

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Error Checking for Sparse Systolic Tensor Arrays., , and . CoRR, (2024)ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining., , , , and . CoRR, (2022)DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity., , , and . CoRR, (2024)The Case for Asymmetric Systolic Array Floorplanning., , , and . CoRR, (2023)Exploiting data encoding and reordering for low-power streaming in systolic arrays., , , and . Microprocess. Microsystems, (2023)FusedGCN: A Systolic Three-Matrix Multiplication Architecture for Graph Convolutional Networks., , , and . ASAP, page 93-97. IEEE, (2022)Low-Power Data Streaming in Systolic Arrays with Bus-Invert Coding and Zero-Value Clock Gating., , , and . MOCAST, page 1-4. IEEE, (2023)Reusing Softmax Hardware Unit for GELU Computation in Transformers., , and . CoRR, (2024)IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications., , , , and . CoRR, (2023)Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines., , , and . AICAS, page 1-5. IEEE, (2023)