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Process-Variation-Aware Adaptive Cache Architecture and Management.

M. Mutyam, F. Wang, K. Ramakrishnan, V. Narayanan, M. Kandemir, Y. Xie, and M. Irwin. IEEE Trans. Computers, 58 (7): 865-877 (2009)

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P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

Other publications of authors with the same name

Managing Leakage Energy in Cache Hierarchies.L. Li, I. Kadayif, Y. Tsai, N. Vijaykrishnan, M. Kandemir, M. Irwin, and A. Sivasubramaniam. J. Instruction-Level Parallelism, (2003)Design considerations for databus charge recovery.B. Bishop, V. Lyuboslavsky, N. Vijaykrishnan, and M. Irwin. IEEE Trans. Very Large Scale Integr. Syst., 9 (1): 104-106 (2001)A clock power model to evaluate impact of architectural and technology optimizations.D. Duarte, N. Vijaykrishnan, and M. Irwin. IEEE Trans. Very Large Scale Integr. Syst., 10 (6): 844-855 (2002)Harnessing ferroelectrics for non-volatile memories and logic.S. Gupta, D. Wang, S. George, A. Aziz, X. Li, S. Datta, and V. Narayanan. ISQED, page 29-34. IEEE, (2017)On the Effects of Process Variation in Network-on-Chip Architectures.C. Nicopoulos, S. Srinivasan, A. Yanamandra, D. Park, V. Narayanan, C. Das, and M. Irwin. IEEE Trans. Dependable Secur. Comput., 7 (3): 240-254 (2010)Java Runtime Systems: Characterization and Architectural Implications.R. Radhakrishnan, N. Vijaykrishnan, L. John, A. Sivasubramaniam, J. Rubio, and J. Sabarinathan. IEEE Trans. Computers, 50 (2): 131-146 (2001)X-VS: Crossbar-Based Processing-in-Memory Architecture for Video Summarization.N. Challapalle, M. Chandran, S. Rampalli, and V. Narayanan. ISVLSI, page 592-597. IEEE, (2020)On the Detection of Clones in Sensor Networks Using Random Key Predistribution.R. Brooks, P. Govindaraju, M. Pirretti, N. Vijaykrishnan, and M. Kandemir. IEEE Trans. Syst. Man Cybern. Part C, 37 (6): 1246-1258 (2007)An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators.N. Gala, S. Krithivasan, W. Tsai, X. Li, V. Narayanan, and V. Kamakoti. ACM J. Emerg. Technol. Comput. Syst., 14 (1): 1:1-1:28 (2018)Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling.S. Yang, P. Gupta, M. Wolf, D. Serpanos, V. Narayanan, and Y. Xie. ACM Trans. Embed. Comput. Syst., 11 (3): 62:1-62:16 (2012)

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Disambiguation of "Narayanan, Vijaykrishnan"

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Process-Variation-Aware Adaptive Cache Architecture and Management.

Please choose a person to relate this publication to

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Narayanan, Vijaykrishnan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Process-Variation-Aware Adaptive Cache Architecture and Management.

Please choose a person to relate this publication to

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Process-Variation-Aware Adaptive Cache Architecture and Management.