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Disambiguation of "Onizawa, Naoya"

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Analog-to-stochastic converter using magnetic-tunnel junction devices.

, , , and . NANOARCH, page 59-64. IEEE Computer Society/ACM, (2014)

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Naoya Koseki

 

Other publications of authors with the same name

Asynchronous Stochastic Decoding of LDPC Codes: Algorithm and Simulation Model., , , and . IEICE Trans. Inf. Syst., 97-D (9): 2286-2295 (2014)High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving., , and . IEICE Trans. Electron., 92-C (6): 867-874 (2009)High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (3): 865-876 (2014)High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip., and . ISCAS, page 157-160. IEEE, (2010)Fast Hardware-based Learning Algorithm for Binarized Perceptrons using CMOS Invertible Logic., , and . FLAP, 7 (1): 41-58 (2020)Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (1): 67-76 (2021)VLSI implementation of deep neural networks using integral stochastic computing., , , , and . ISTC, page 216-220. IEEE, (2016)Design of an STT-MTJ based true random number generator using digitally controlled probability-locked loop., , , and . NEWCAS, page 1-4. IEEE, (2015)Stochastic-Computing Based Brainwave LSI Towards an Intelligence Edge., , and . ICECS, page 434-437. IEEE, (2019)FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic., , and . ICECS, page 115-116. IEEE, (2019)