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A Hardware-Efficient Logarithmic Multiplier with Improved Accuracy., , and . DATE, page 928-931. IEEE, (2019)A novel gate grading approach for soft error tolerance in combinational circuits., , , and . CCECE, page 1-4. IEEE, (2016)Design and evaluation of stochastic FIR filters., , , and . PACRIM, page 407-412. IEEE, (2015)Efficient architectures for 1-D and 2-D lifting-based wavelet transforms., , and . IEEE Trans. Signal Process., 52 (5): 1315-1326 (2004)Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM., , , , and . MTDT, page 117-122. IEEE Computer Society, (2002)An Investigation into Crosstalk Noise in DRAM Structures., , and . MTDT, page 123-. IEEE Computer Society, (2002)Stochastic circuit design and performance evaluation of vector quantization., , , and . ASAP, page 111-115. IEEE Computer Society, (2015)Near-optimal and efficient MIMO detectors for 64-QAM symbols., and . CCECE, page 1-6. IEEE, (2010)A Logarithmic Floating-Point Multiplier for the Efficient Training of Neural Networks., , , , , and . ACM Great Lakes Symposium on VLSI, page 65-70. ACM, (2021)Design and Evaluation of an FPGA-based Hardware Accelerator for Deflate Data Decompression., , and . CCECE, page 1-6. IEEE, (2019)