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Disambiguation of "Wu, Ssu-Yen"

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15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.

, , , , , , , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 246-248. IEEE, (2020)

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Per-yen Wu

Wu per-yen

Yen-cheng Wu

Yen-Ying Stephanie Wu

Yen Yen Kwan

 

Other publications of authors with the same name

13.4 A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices., , , , , , , , , and 2 other author(s). ISSCC, page 224-226. IEEE, (2020)A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning., , , , , , , , , and 6 other author(s). ISSCC, page 396-398. IEEE, (2019)A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 57 (6): 1936-1949 (2022)Use of accelerometers to detect motor states in a seizure of rats with temporal lobe epilepsy., , , , , and . BioCAS, page 372-375. IEEE, (2012)Detection of spontaneous temporal lobe epilepsy in rats by means of 1-axis accelerometor signal., , , , and . ICICS, page 1-5. IEEE, (2013)A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 55 (1): 189-202 (2020)A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips., , , , , , , , , and 11 other author(s). IEEE J. Solid State Circuits, 56 (9): 2817-2831 (2021)A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS., , , , , , , , , and 3 other author(s). VLSI Circuits, page 120-. IEEE, (2019)15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips., , , , , , , , , and 17 other author(s). ISSCC, page 246-248. IEEE, (2020)