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Disambiguation of "Su, Jian-Wei"

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15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.

, , , , , , , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 246-248. IEEE, (2020)

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Jian Su

Wei Jian

Hao-Wei Su

Su-Wei Tan

Jian-Wei Liu

 

Other publications of authors with the same name

Cross-Layer Optimizations in Solid-State Drives., , , and . IEEE Embed. Syst. Lett., 3 (4): 109-112 (2011)Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips., , , , , , , , , and 15 other author(s). IEEE J. Solid State Circuits, 57 (2): 609-624 (2022)A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 59 (1): 196-207 (January 2024)Circuit Design Challenges in Computing-in-Memory for AI Edge Devices., , , , , , , , , and 1 other author(s). ASICON, page 1-4. IEEE, (2019)A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices., , , , , , , , , and 7 other author(s). ISSCC, page 126-127. IEEE, (2023)A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating., , , , , , , , , and 7 other author(s). ISSCC, page 238-240. IEEE, (2021)15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips., , , , , , , , , and 13 other author(s). ISSCC, page 240-242. IEEE, (2020)A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 55 (10): 2790-2801 (2020)34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices., , , , , , , , , and 5 other author(s). ISSCC, page 568-570. IEEE, (2024)A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration., , , , , , , , , and . A-SSCC, page 1-3. IEEE, (2021)