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Disambiguation of "Weber, Serge"

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A Multi-Application, Scalable and Adaptable Hardware SOM Architecture.

, , , , and . IJCNN, page 1-8. IEEE, (2019)

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Elena Sergeyev

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Other publications of authors with the same name

High performance scalable hardware SOM architecture for real-time vector quantization., , and . IPAS, page 256-261. IEEE, (2018)State-Space Simulation of Electric Arc Faults., , , and . IEEE Trans. Aerosp. Electron. Syst., 58 (3): 1650-1659 (2022)Scalable, dynamic and growing hardware self-organizing architecture for real-time vector quantization., , , , and . ICECS, page 1-4. IEEE, (2020)A Multi-Application, Scalable and Adaptable Hardware SOM Architecture., , , , and . IJCNN, page 1-8. IEEE, (2019)Cluster-Based Hybrid Reconfigurable Architecture for Auto-adaptive SoC., , and . ICECS, page 979-982. IEEE, (2007)Automated RTR Temporal Partitioning for Reconfigurable Embedded Real-Time System Design., , , and . IPDPS, page 178. IEEE Computer Society, (2003)VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher., , , , and . DELTA, page 386-389. IEEE Computer Society, (2008)SIMD/restricted MIMD parallel architecture for Image Processing Based on a New Design of a Multi-mode Access Memory., , , and . PDPTA, page 567-570. CSREA Press, (1999)Linear array processors with multiple access modes memory for real-time image processing., , , , and . APCCAS (1), page 203-206. IEEE, (2002)A Partitioning Methodology That Optimises the Area on Reconfigurable Real-Time Embedded Systems., , , and . EURASIP J. Adv. Signal Process., 2003 (6): 494-501 (2003)