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Disambiguation of "Berviller, Yves"

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Automated RTR Temporal Partitioning for Reconfigurable Embedded Real-Time System Design.

, , , and . IPDPS, page 178. IEEE Computer Society, (2003)

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Yves Burkhardt

Yves Gensterblum

Yves Matthess

Yves Steinmetz

Yves Hoffmann

 

Other publications of authors with the same name

Medical image denoising on field programmable gate array using finite Radon transform., , , and . IET Signal Process., 6 (9): 862-870 (2012)Automated RTR Temporal Partitioning for Reconfigurable Embedded Real-Time System Design., , , and . IPDPS, page 178. IEEE Computer Society, (2003)Hardware Partitioning Software for Dynamically Reconfigurable SoC Design., , , and . IWSOC, page 106-111. IEEE Computer Society, (2003)Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system., , , , and . Microprocess. Microsystems, 27 (3): 115-130 (2003)Contextual Detection of Pedestrians and Vehicles in Orthophotography by Fusion of Deep Learning Algorithms., , , , and . Sensors, 22 (4): 1381 (2022)A Design Methodology for Power Electronics Digital Control based on an FPGA in the Loop Prototyping., , , and . ICECS, page 701-704. IEEE, (2007)A Partitioning Methodology That Optimises the Area on Reconfigurable Real-Time Embedded Systems., , , and . EURASIP J. Adv. Signal Process., 2003 (6): 494-501 (2003)Optimization of Motion Estimator for Run-Time-Reconfiguration Implementation., , and . IPDPS Workshops, volume 1800 of Lecture Notes in Computer Science, page 959-965. Springer, (2000)An Embedded and Programmable System Based FPGA for Real Time MPEG Stream Buffer Analysis., , , , , and . IEEE Trans. Circuits Syst. Video Technol., 19 (2): 237-249 (2009)FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding., , , , and . SoCC, page 423-426. IEEE, (2009)