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Disambiguation of "Ryu, Sigang"

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A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs.

, , , , , and . ISCAS, page 754-757. IEEE, (2012)

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Sigang Qin

Ryu Yoshiwhara

Hosuk Ryu

Stella Ryu

Ryu Saito

 

Other publications of authors with the same name

A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications., , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (3): 1245-1257 (2019)A 2 × Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery., , , and . IEEE J. Solid State Circuits, 54 (10): 2823-2832 (2019)A Time-Based Pipelined ADC Using Integrate-and-Fire Multiplying-DAC., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (7): 2876-2889 (2021)A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function., , , , and . IEEE J. Solid State Circuits, 49 (8): 1773-1784 (2014)A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs., , , , , and . ISCAS, page 754-757. IEEE, (2012)A Scalable Platform for Single-Snapshot Direction Of Arrival (DOA) Estimation in Massive MIMO Systems., , , and . ACM Great Lakes Symposium on VLSI, page 631-637. ACM, (2023)13.1 A 940MHz-bandwidth 28.8µs-period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications., , , , and . ISSCC, page 238-239. IEEE, (2016)A 2× Blind Oversampling FSE Receiver with Combined Adaptive Equalization and Infinite-Range Timing Recovery., , , and . A-SSCC, page 201-204. IEEE, (2018)A 9.2-GHz digital phase-locked loop with peaking-free transfer function., , , , and . CICC, page 1-4. IEEE, (2013)