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Stochastic SOT Device Based SNN Architecture for On-Chip Unsupervised STDP Learning.

, , , , , , and . IEEE Trans. Computers, 71 (9): 2022-2035 (2022)

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Fast and Disturb-Free Nonvolatile Flip-Flop Using Complementary Polarizer MTJ., , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (4): 1573-1577 (2017)Stochastic SOT Device Based SNN Architecture for On-Chip Unsupervised STDP Learning., , , , , , and . IEEE Trans. Computers, 71 (9): 2022-2035 (2022)High-Density SOT-MRAM Based on Shared Bitline Structure., and . IEEE Trans. Very Large Scale Integr. Syst., 26 (8): 1600-1603 (2018)Layout-Aware Area Optimization of Transposable STT-MRAM for a Processing-In-Memory System., , , and . IEEE Trans. Very Large Scale Integr. Syst., 32 (2): 245-255 (February 2024)Area-optimized design of SOT-MRAM., and . IEICE Electron. Express, 17 (21): 20200314 (2020)High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 293-304 (2016)Dynamic-Reference Based Early Write Termination for Low Energy SOT-MRAM., , , , and . ISCAS, page 1-5. IEEE, (2020)Automation Framework for Digital Circuit Design and Verification., , and . ISOCC, page 263-264. IEEE, (2022)