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Design space exploration of FPGA accelerators for convolutional neural networks.

, , , and . DATE, page 1147-1152. IEEE, (2017)

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Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design., , and . FPGA, page 247. ACM, (1999)Concept-aware ensemble system for pedestrian detection., , and . Intelligent Vehicles Symposium, page 140-145. IEEE, (2014)A deadlock-free routing algorithm requiring no virtual channel on 3D-NoCs with partial vertical connections., and . NOCS, page 1-2. IEEE, (2013)Message from the general chairs., and . VLSI-SoC, page VIII. IEEE, (2015)Dynamic error tracking and supply voltage adjustment for low power., and . VLSI-SoC, page 74-79. IEEE, (2015)THOR: Orchestrated thermal management of cores and networks in 3D many-core architectures., , , and . ASP-DAC, page 773-778. IEEE, (2015)Memory-aware mapping and scheduling of tasks and communications on many-core SoC., and . ASP-DAC, page 419-424. IEEE, (2012)Resonant properties of piezoelectric cantilever transducers fabricated on the SiC membrane., , , , and . NEMS, page 61-63. IEEE, (2011)Performance improvement of geographically distributed cosimulation by hierarchically grouped messages., , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (5): 492-502 (2000)Partial bus-invert coding for power optimization of application-specific systems., , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (2): 377-383 (2001)