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Low-Power and testable circuit synthesis using Shannon decomposition.

, , and . ACM Trans. Design Autom. Electr. Syst., 12 (4): 47 (2007)

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Attack resilient architecture to replace embedded Flash with STTRAM in homogeneous IoTs., , and . CoRR, (2016)A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support., , , , , , , , , and 3 other author(s). ISLPED, page 34:1-34:6. ACM, (2018)Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing., , and . JETC, 14 (1): 8:1-8:17 (2018)Addressing Resiliency of In-Memory Floating Point Computation., , , and . CoRR, (2020)Quantum-Soft QUBO Suppression for Accurate Object Detection., and . ECCV (29), volume 12374 of Lecture Notes in Computer Science, page 158-173. Springer, (2020)Addressing Resiliency of In-Memory Floating Point Computation., , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (9): 1172-1183 (2022)Energy centric model of SRAM write operation for improved energy and error rates.. CICC, page 1-4. IEEE, (2013)FIXER: Flow Integrity Extensions for Embedded RISC-V., , , and . DATE, page 348-353. IEEE, (2019)iMACE: In-Memory Acceleration of Classic McEliece Encoder., , , , and . ISVLSI, page 513-518. IEEE, (2019)HeapSafe: Securing Unprotected Heaps in RISC-V., and . CoRR, (2021)