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Disambiguation of "Tanzawa, Toru"

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A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller.

, , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 37 (11): 1485-1492 (2002)

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Toru Nomura

Toru Matsuyama

Toru Kashima

Richard Heinrich Torunsky

Ahmet Refah Torun

 

Other publications of authors with the same name

A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 37 (11): 1485-1492 (2002)Optimization of word-line booster circuits for low-voltage flash memories., and . IEEE J. Solid State Circuits, 34 (8): 1091-1098 (1999)A Circuit Analysis of Pre-Emphasis Pulses for RC Delay Lines., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 104-A (6): 912-926 (2021)On-chip switched-capacitor DC-DC converter in memory technology: State of the art and challenges.. ECCTD, page 1-4. IEEE, (2017)A process- and temperature-tolerant power-on reset circuit with a flexible detection level higher than the bandgap voltage.. ISCAS, page 2302-2305. IEEE, (2008)Circuit techniques for a 1.8-V-only NAND flash memory., , , and . IEEE J. Solid State Circuits, 37 (1): 84-89 (2002)A Charge Loss Aware Advanced Model of Dickson Voltage Multipliers., , , and . IEEE Access, (2022)An Analytical Model of Charge Pump DC-DC Voltage Multiplier Using Diodes.. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (5): 1137-1144 (2017)A Pre-Emphasis Pulse Generator Insensitive to Process Variation for Driving Large Memory and Panel Display Arrays with Minimal Delay Time., and . APCCAS, page 45-48. IEEE, (2019)A 172mm2 32Gb MLC NAND flash memory in 34nm CMOS., , , , , , , , , and 24 other author(s). ISSCC, page 236-237. IEEE, (2009)