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Disambiguation of "Taura, Tadayuki"

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A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller.

, , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 37 (11): 1485-1492 (2002)

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Daniel Taurat

Olaf Tauras

Bernhard Taurat

 

Other publications of authors with the same name

A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 37 (11): 1485-1492 (2002)An 83dB-dynamic-range single-exposure global-shutter CMOS image sensor with in-pixel dual storage., , , , , , , , , and 8 other author(s). ISSCC, page 380-382. IEEE, (2012)A 6.9 μm Pixel-Pitch 3D Stacked Global Shutter CMOS Image Sensor with 3M Cu-Cu connections., , , , , , and . 3DIC, page 1-2. IEEE, (2019)A back-illuminated global-shutter CMOS image sensor with pixel-parallel 14b subthreshold ADC., , , , , , , , , and 13 other author(s). ISSCC, page 80-82. IEEE, (2018)Wordline voltage generating system for low-power low-voltage flash memories., , , , , , , , and . IEEE J. Solid State Circuits, 36 (1): 55-63 (2001)A 6.9-µm Pixel-Pitch Back-Illuminated Global Shutter CMOS Image Sensor With Pixel-Parallel 14-Bit Subthreshold ADC., , , , , , , , , and 11 other author(s). IEEE J. Solid State Circuits, 53 (11): 3017-3025 (2018)A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 35 (11): 1648-1654 (2000)Design of a sense circuit for low-voltage flash memories., , , and . IEEE J. Solid State Circuits, 35 (10): 1415-1421 (2000)High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor., , , , , , , , , and 3 other author(s). ISSCC, page 2024-2031. IEEE, (2006)