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DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.

, , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (4): 748-761 (2021)

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DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement., , , , , and . DAC, page 117. ACM, (2019)DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (4): 748-761 (2021)UTPlaceF 3.0: A parallelization framework for modern FPGA global placement: (Invited paper)., , , and . ICCAD, page 922-928. IEEE, (2017)A New Paradigm for FPGA Placement Without Explicit Packing., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (11): 2113-2126 (2019)Systolic Array Placement on FPGAs., , , , and . ICCAD, page 1-9. IEEE, (2023)FLOPS: EFficient On-Chip Learning for OPtical Neural Networks Through Stochastic Zeroth-Order Optimization., , , , , and . DAC, page 1-6. IEEE, (2020)elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs., , and . ICCAD, page 1-8. ACM, (2019)elfPlace: Electrostatics-Based Placement for Large-Scale Heterogeneous FPGAs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (1): 155-168 (2022)ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 5083-5096 (2020)UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine., , , , and . ACM Trans. Design Autom. Electr. Syst., 23 (4): 42:1-42:23 (2018)