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Disambiguation of "Dhar, Shounak"

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DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.

, , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (4): 748-761 (2021)

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Tulika Dhar

Rajkumar Dhar

Asok Dhar

Jawaharlal Dhar

Elavarasi Dharmalingam

Coordination of membran cytoskeleton interactions: role of syndapins and Abp 1 = Koordination von Membran-Zytoskelett-Interaktionen. Uni Jena, (2009)
 

Other publications of authors with the same name

GDP: GPU accelerated Detailed Placement., and . HPEC, page 1-7. IEEE, (2018)DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (4): 748-761 (2021)An Effective Timing-Driven Detailed Placement Algorithm for FPGAs., , , , , and . ISPD, page 151-157. ACM, (2017)DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement., , , , , and . DAC, page 117. ACM, (2019)A shape-driven spreading algorithm using linear programming for global placement., , , and . ASP-DAC, page 563-568. ACM, (2019)Optical computing on silicon-on-insulator-based photonic integrated circuits., , , , , and . ASICON, page 472-475. IEEE, (2017)UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (4): 869-882 (2018)UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packing., , and . ICCAD, page 66. ACM, (2016)Detailed placement for modern FPGAs using 2D dynamic programming., , , , and . ICCAD, page 9. ACM, (2016)FPGA Accelerated FPGA Placement., , , and . FPL, page 404-410. IEEE, (2019)