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Disambiguation of "Narayanan, Vijaykrishnan"

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The 4th Artificial Intelligence of Things (AIoT) Workshop.

, , , , , , , , , and . KDD, page 4179-4180. ACM, (2021)

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P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

 

Other publications of authors with the same name

A scalable architecture for multi-class visual object detection., , , , and . FPL, page 1-8. IEEE, (2015)A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support., , , , , , , , , and 3 other author(s). ISLPED, page 34:1-34:6. ACM, (2018)Process-Variation-Aware Adaptive Cache Architecture and Management., , , , , , and . IEEE Trans. Computers, 58 (7): 865-877 (2009)A reconfigurable platform for the design and verification of domain-specific accelerators., , , and . ASP-DAC, page 108-113. IEEE, (2012)Clone Detection in Sensor Networks with Ad Hoc and Grid Topologies., , , , and . IJDSN, 5 (3): 209-223 (2009)A hardware accelerated multilevel visual classifier for embedded visual-assist systems., , , , and . ICCAD, page 96-100. IEEE, (2014)FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access With Reduced Bitline Charging Activity and Recycled Bitline Charge., , , , , , , , , and 1 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 70 (6): 2398-2411 (2023)A compiler-based approach for dynamically managing scratch-pad memories in embedded systems., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (2): 243-260 (2004)Hardware Functional Obfuscation With Ferroelectric Active Interconnects., , , , , , , , , and 1 other author(s). CoRR, (2021)Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications., , , , , , and . IEEE Micro, 35 (5): 32-40 (2015)