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Locality &\#38; utility co-optimization for practical capacity management of shared last level caches

, , and . Proceedings of the 26th ACM international conference on Supercomputing, page 279--290. New York, NY, USA, ACM, (2012)
DOI: 10.1145/2304576.2304615

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A Novel Method to Improve the Test Efficiency of VLSI Tests., , and . ASP-DAC/VLSI Design, page 499-504. IEEE Computer Society, (2002)Improving Circuit Testability by Clock Control., , and . Great Lakes Symposium on VLSI, page 288-293. IEEE Computer Society, (1996)Leverage Redundancy in Hardware Transactional Memory to Improve Cache Reliability., , , , and . ICPP, page 60:1-60:10. ACM, (2018)A fast fault simulation algorithm for combinational circuits., , and . ICCAD, page 166-169. IEEE Computer Society, (1988)Energy-efficient I/O Thread Schedulers for NVMe SSDs on NUMA., , , , , and . CCGrid, page 569-578. IEEE Computer Society / ACM, (2017)A nonparametric classifier for unsegmented text., , , , , , and . DRR, volume 5296 of SPIE Proceedings, page 102-108. SPIE, (2004)Predicting Fault Coverage from Probabilistic Testability.. ITC, page 803-807. IEEE Computer Society, (1985)Clock partitioning for testability., , and . Great Lakes Symposium on VLSI, page 42-46. IEEE, (1993)High-level microprogramming: an optimizing C compiler for a processing element of a CAD accelerator., , and . MICRO, page 97-106. ACM/IEEE, (1990)Estimating the Quality of Manufactured Digital Sequential Circuits., , and . ITC, page 210-217. IEEE Computer Society, (1991)