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An efficient compiler framework for cache bypassing on GPUs., , , and . ICCAD, page 516-523. IEEE, (2013)Optimal reference subset selection for nearest neighbor classification by tabu search., and . Pattern Recognit., 35 (7): 1481-1490 (2002)Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power., , , , , and . ASP-DAC, page 100-105. IEEE, (2015)Fabrication cost analysis for 2D, 2.5D, and 3D IC designs., and . 3DIC, page 1-4. IEEE, (2011)Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory., , , and . JETC, 9 (3): 22:1-22:22 (2013)NoC-Sprinting: Interconnect for Fine-Grained Sprinting in the Dark Silicon Era., , and . DAC, page 160:1-160:6. ACM, (2014)Three-dimensional Integrated Circuits: Design, EDA, and Architecture., , , , and . Foundations and Trends in Electronic Design Automation, 5 (1-2): 1-151 (2011)Performance-centric register file design for GPUs using racetrack memory., , , , , , , and . ASP-DAC, page 25-30. IEEE, (2016)GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (4): 640-653 (2019)COPPER: a combinatorial optimization problem solver with processing-in-memory architecture., , , , , , and . Frontiers Inf. Technol. Electron. Eng., 24 (5): 731-741 (May 2023)