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Disambiguation of "Miki, Takuji"

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An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects.

, , , and . IEEE J. Solid State Circuits, 47 (11): 2773-2782 (2012)

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Takuji Shimano

Miki Tsukada

Takuji Kadowaki

ivko Miki

Nicole Mikisch

 

Other publications of authors with the same name

Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging., , , , , , , , , and . IEICE Trans. Electron., 106 (10): 556-564 (October 2023)Physical Attack Protection Techniques for IC Chip Level Hardware Security., , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (1): 5-14 (2022)Characterization of Backside ESD Impacts on Integrated Circuits., , , , , and . IRPS, page 1-6. IEEE, (2023)Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs., , , , , , , , and . 3DIC, page 1-4. IEEE, (2019)On-Chip Physical Attack Protection Circuits for Hardware Security : Invited Paper., , and . CICC, page 1-6. IEEE, (2019)A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan., , , , , , and . IEEE J. Solid State Circuits, 50 (11): 2741-2749 (2015)A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices., , , , , , , , and . A-SSCC, page 25-28. IEEE, (2019)A Triturated Sensing System., , , , , , , and . ISSCC, page 216-217. IEEE, (2023)A 97.99 dB SNDR, 2 kHz BW, 37.1 µW noise-shaping SAR ADC with dynamic element matching and modulation dither effect., , , , and . VLSI Circuits, page 1-2. IEEE, (2016)A 2-GS/s 8-bit Time-Interleaved SAR ADC for Millimeter-Wave Pulsed Radar Baseband SoC., , and . IEEE J. Solid State Circuits, 52 (10): 2712-2720 (2017)