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High-mobility high-Ge-content Si1-xGex-OI PMOS FinFETs with fins formed using 3D germanium condensation with Ge fraction up to x∼ 0.7, scaled EOT∼8.5Å and ∼10nm fin width.

P. Hashemi, T. Ando, K. Balakrishnan, J. Bruley, S. Engelmann, J. Ott, V. Narayanan, D. Park, R. Mo, and E. Leobandung. VLSIC, page 16-. IEEE, (2015)

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Vijay Narayanan Swaminathan

Balakumar Vijayakrishnan

Vijay Divi

Vijay Singh

P Narayanan

Other publications of authors with the same name

Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators.M. Rasch, C. Mackin, M. Gallo, A. Chen, A. Fasoli, F. Odermatt, N. Li, S. Nandakumar, P. Narayanan, H. Tsai and 3 other author(s). CoRR, (2023)PBTI in InGaAs MOS capacitors with Al2O3/HfO2/TiN gate stacks: Interface-state generation.E. Cartier, M. Frank, T. Ando, J. Rozen, and V. Narayanan. IRPS, page 5. IEEE, (2018)In-memory Realization of In-situ Few-shot Continual Learning with a Dynamically Evolving Explicit Memory.G. Karunaratne, M. Hersche, J. Langenegger, G. Cherubini, M. Gallo, U. Egger, K. Brew, S. Choi, I. Ok, M. Silvestre and 8 other author(s). CoRR, (2022)3D GPU architecture using cache stacking: Performance, cost, power and thermal analysis.A. Al-Maashri, G. Sun, X. Dong, V. Narayanan, and Y. Xie. ICCD, page 254-259. IEEE Computer Society, (2009)Interface engineering of Si1-xGex gate stacks for high performance dual channel CMOS.C. Lee, R. Southwick, S. Mochizuki, P. Jamison, R. Bao, R. Pandey, A. Konar, T. Ando, V. Narayanan, B. Haran and 1 other author(s). ASICON, page 573-576. IEEE, (2017)Gradient descent-based programming of analog in-memory computing cores.J. Büchel, A. Vasilopoulos, B. Kersting, F. Odermatt, K. Brew, I. Ok, S. Choi, I. Saraf, V. Chan, T. Philip and 4 other author(s). CoRR, (2023)Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited).M. Frank, N. Li, M. Rasch, S. Jain, C. Chen, R. Muralidhar, J. Han, V. Narayanan, T. Philip, K. Brew and 11 other author(s). IRPS, page 1-10. IEEE, (2023)Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited).G. Burr, P. Narayanan, S. Ambrogio, A. Okazaki, H. Tsai, K. Hosokawa, C. Mackin, A. Nomura, T. Yasuda, J. Demarest and 15 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Characterizing the soft error vulnerability of multicores running multithreaded applications.N. Soundararajan, A. Sivasubramaniam, and V. Narayanan. SIGMETRICS, page 379-380. ACM, (2010)AnalogNAS: A Neural Network Design Framework for Accurate Inference with Analog In-Memory Computing.H. Benmeziane, C. Lammie, I. Boybat, M. Rasch, M. Gallo, H. Tsai, R. Muralidhar, S. Niar, H. Ouarnoughi, V. Narayanan and 2 other author(s). EDGE, page 233-244. IEEE, (2023)

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Disambiguation of "Narayanan, Vijay"