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Disambiguation of "Palesi, Maurizio"

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Efficient Congestion-Aware Scheme for Wireless on-Chip Networks.

, , , and . PDP, page 742-749. IEEE Computer Society, (2016)

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Maurizio Podda

Maurizio Venturini

Maurizio Zanazzi

Maurizio Podda

Maurizio Serva

 

Other publications of authors with the same name

Guest Editors' Introduction to the Special Issue on "Novel On-Chip Parallel Architectures and Software Support"., , and . Parallel Comput., 39 (9): 355-356 (2013)Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip., , , , and . J. Comput. Sci., 11 (3): 552-566 (2015)Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices., , , , , and . IoTSMS, page 227-234. IEEE, (2019)Efficient design space exploration for application specific systems-on-a-chip., , , , and . J. Syst. Archit., 53 (10): 733-750 (2007)Bandwidth-aware routing algorithms for networks-on-chip platforms., , and . IET Comput. Digit. Tech., 3 (5): 413-429 (2009)Local Congestion Avoidance in Network-on-Chip., , and . IEEE Trans. Parallel Distributed Syst., 27 (7): 2062-2073 (2016)Cloud-Based Energy Efficient Scheme for Sigfox Monarch as Asset Tracking Service., , , and . COINS, page 1-6. IEEE, (2020)Data Encoding Schemes in Networks on Chip., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (5): 774-786 (2011)A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (4): 635-645 (2005)Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks-on-Chip., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (3): 426-440 (2010)