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An Enhanced Service Provider Communication Interface with Client Prioritization - Case Study on Fast-food Chain Restaurants.

, , and . ICE-B, page 197-202. INSTICC Press, (2008)

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A Fast and Scalable Pipeline for Stain Normalization of Whole-Slide Images in Histopathology., , , , , , , , and . ECCV Workshops (6), volume 11134 of Lecture Notes in Computer Science, page 424-436. Springer, (2018)Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density., , , , and . ACM Great Lakes Symposium on VLSI, page 204-207. ACM, (2007)Output probability density functions of logic circuits: Modeling and fault-tolerance evaluation., , and . VLSI-SoC, page 328-334. IEEE, (2010)Multilevel-Cell Phase-Change Memory: A Viable Technology., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (1): 87-100 (2016)Phase-change memory: Feasibility of reliable multilevel-cell storage and retention at elevated temperatures., , , , and . IRPS, page 5. IEEE, (2015)Acceleration of Decision-Tree Ensemble Models on the IBM Telum Processor., , , , , , , , , and 1 other author(s). ISCAS, page 1-5. IEEE, (2023)Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density., , and . IJCNN, page 2771-2778. IEEE, (2006)A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh., , , , , , , , , and 5 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 31 (1): 114-127 (2023)HERMES-Core - A 1.59-TOPS/mm2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs., , , , , , , , , and 14 other author(s). IEEE J. Solid State Circuits, 57 (4): 1027-1038 (2022)Circuit and System-Level Aspects of Phase Change Memory., , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (3): 844-850 (2021)