Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Physical synthesis of bus matrix for high bandwidth low power on-chip communications.

R. Wang, E. Young, R. Graham, and C. Cheng. ISPD, page 91-96. ACM, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Wang Wang

Linfang Wang

Investigation of the functions of 53BP1 in DNA demethylationL. Wang. Uni Marburg, (2009)

Paul Wang

Lien Wang

Scheifoo Wang

Other publications of authors with the same name

Physical planning to embrace interconnect dominance in power and performance.R. Wang. University of California, San Diego, USA, (2010)Post-OCR Paragraph Recognition by Graph Convolutional Networks.R. Wang, Y. Fujii, and A. Popat. WACV, page 2533-2542. IEEE, (2022)General-Purpose OCR Paragraph Identification by Graph Convolution Networks.R. Wang, Y. Fujii, and A. Popat. CoRR, (2021)ROPE: Reading Order Equivariant Positional Encoding for Graph-based Document Information Extraction.C. Lee, C. Li, C. Wang, R. Wang, Y. Fujii, S. Qin, A. Popat, and T. Pfister. ACL/IJCNLP (2), page 314-321. Association for Computational Linguistics, (2021)Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations.R. Wang, T. Okamoto, and C. Cheng. ICCD, page 23-28. IEEE Computer Society, (2009)Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness.R. Wang, E. Young, and C. Cheng. ACM Trans. Design Autom. Electr. Syst., 15 (4): 33:1-33:22 (2010)Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications.R. Wang, N. Chou, B. Salefski, and C. Cheng. DAC, page 166-171. ACM, (2009)Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip.R. Wang, and N. Shah. ISPD, page 187-192. ACM, (2012)On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design.R. Wang, and C. Cheng. ACM Great Lakes Symposium on VLSI, page 257-262. ACM, (2009)Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications.R. Wang, Y. Zhang, N. Chou, E. Young, C. Cheng, and R. Graham. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (2): 167-179 (2011)

BibSonomy

Disambiguation of "Wang, Renshen"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Physical synthesis of bus matrix for high bandwidth low power on-chip communications.

Please choose a person to relate this publication to

Wang Wang

Linfang Wang

Paul Wang

Lien Wang

Scheifoo Wang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wang, Renshen"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Physical synthesis of bus matrix for high bandwidth low power on-chip communications.

Please choose a person to relate this publication to

Wang Wang

Linfang Wang

Paul Wang

Lien Wang

Scheifoo Wang

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Physical synthesis of bus matrix for high bandwidth low power on-chip communications.