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Disambiguation of "Reorda, Matteo Sonza"

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On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (4): 813-823 (2014)

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Matteo Rini

Matteo Garavoglia

Matteo Bertini

Matteo Gabba

Marco Matteo

 

Other publications of authors with the same name

Test-Plan Optimization for Flying-Probes In-Circuit Testers., , , and . ITC-Asia, page 19-24. IEEE, (2019)A Novel Sequence Generation Approach to Diagnose Faults in Reconfigurable Scan Networks., , , and . IEEE Trans. Computers, 69 (1): 87-98 (2020)Software-Based Self-Test for Transition Faults: a Case Study., , , and . VLSI-SoC, page 76-81. IEEE, (2019)New techniques for efficiently assessing reliability of SOCs., , , , and . Microelectron. J., 34 (1): 53-61 (2003)On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors., , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (4): 813-823 (2014)RT-Level ITC'99 Benchmarks and First ATPG Results., , and . IEEE Des. Test Comput., 17 (3): 44-53 (2000)System-level test bench generation in a co-design framework., , , , and . ETW, page 25-30. IEEE Computer Society, (2000)DYRE: a DYnamic REconfigurable solution to increase GPGPU's reliability., , , and . J. Supercomput., 77 (10): 11625-11642 (2021)Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug., , , and . IET Comput. Digit. Tech., 4 (2): 104-113 (2010)Microprocessor Testing: Functional Meets Structural Test., , , , , and . J. Circuits Syst. Comput., 26 (8): 1740007:1-1740007:18 (2017)