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Breaking the Memory Wall for AI Chip with a New Dimension., , , , , , , , , and 1 other author(s). SEEDA-CECNSM, page 1-7. IEEE, (2020)DRAM-Based Processor for Deep Neural Networks Without SRAM Cache., , , , , , , , , and 1 other author(s). SAI (2), volume 284 of Lecture Notes in Networks and Systems, page 743-753. Springer, (2021)A 16Gb 3b/ Cell NAND Flash Memory in 56nm with 8MB/s Write Rate., , , , , , , , , and 38 other author(s). ISSCC, page 506-507. IEEE, (2008)A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate., , , , , , , , , and 38 other author(s). IEEE J. Solid State Circuits, 44 (1): 195-207 (2009)Pseudo-coevolutionary genetic algorithms for power electronic circuits optimization., , , , , and . IEEE Congress on Evolutionary Computation, page 474-481. IEEE, (2003)