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Binary synthesis implementing external interrupt handler as independent module., , , , и . RSP, стр. 92-98. ACM, (2017)Random testing of C compilers based on test program generation by equivalence transformation., и . APCCAS, стр. 676-679. IEEE, (2016)Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (8): 868-875 (1990)Linear time fault simulation algorithm using a content addressable memory., и . EURO-DAC, стр. 442-445. IEEE Computer Society Press, (1992)Extending equivalence transformation based program generator for random testing of C compilers., , и . A-TEST@ESEC/SIGSOFT FSE, стр. 9-15. ACM, (2018)Speculative execution in distributed controllers for high-level synthesis., , , и . RSP, стр. 99-104. ACM, (2017)Formal semantics of UDL/I and its applications to CAD/DA tools., и . ICCD, стр. 90-94. IEEE Computer Society, (1990)Full Hardware Implementation of FreeRTOS-Based Real-Time Systems., , и . TENCON, стр. 435-440. IEEE, (2021)Breadth-First Manipulation of SBDD of Boolean Functions for Vector Processing., , и . DAC, стр. 413-416. ACM, (1991)Fault Simulation for Multiple Faults Using Shared BDD Representation of Fault Sets., , и . ICCAD, стр. 550-553. IEEE Computer Society, (1991)