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Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation.

, , , , , and . DAC, page 7:1-7:6. ACM, (2016)

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Performance-driven mapping for CPLD architectures., , , and . FPGA, page 39-47. ACM, (2001)Throughput-oriented kernel porting onto FPGAs., , , , and . DAC, page 11:1-11:10. ACM, (2013)Optimality study of resource binding with multi-Vdds., , , and . DAC, page 580-585. ACM, (2006)Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation., , , , , and . DAC, page 7:1-7:6. ACM, (2016)Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices., , , and . SLIP@DAC, page 1:1-1:8. ACM, (2018)Algorithm/Accelerator Co-Design and Co-Search for Edge AI., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (7): 3064-3070 (2022)VecQ: Minimal Loss DNN Model Compression With Vectorized Weight Quantization., , , , , and . IEEE Trans. Computers, 70 (5): 696-710 (2021)ScaleHLS: Scalable High-Level Synthesis through MLIR., , , , , , and . CoRR, (2021)Flexible transition metal dichalcogenide field-effect transistors: A circuit-level simulation study of delay and power under bending, process variation, and scaling., , and . ASP-DAC, page 761-768. IEEE, (2016)Fast large-scale optimal power flow analysis for smart grid through network reduction., and . ASP-DAC, page 373-378. IEEE, (2014)