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Network footprint reduction through data access and computation placement in NoC-based manycores., , , and . DAC, page 181:1-181:6. ACM, (2015)Optimising power efficiency in trace cache fetch unit., , , and . IET Comput. Digit. Tech., 1 (4): 334-348 (2007)Multiverse: Dynamic VM Provisioning for Virtualized High Performance Computing Clusters., , , , , and . CCGRID, page 131-141. IEEE, (2020)Selective Caching: Avoiding Performance Valleys in Massively Parallel Architectures., , and . PDP, page 290-298. IEEE, (2020)Compiler-guided leakage optimization for banked scratch-pad memories., , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (10): 1136-1146 (2005)Energy-Aware Code Replication for Improving Reliability in Embedded Chip Multiprocessors., , , and . SoCC, page 77-78. IEEE, (2006)Soft error and energy consumption interactions: a data cache perspective., , , , and . ISLPED, page 132-137. ACM, (2004)Exploiting program hotspots and code sequentiality for instruction cache leakage management., , , , and . ISLPED, page 402-407. ACM, (2003)Estimating influence of data layout optimizations on SDRAM energy consumption., , , , , and . ISLPED, page 40-43. ACM, (2003)Application mapping for chip multiprocessors., , , and . DAC, page 620-625. ACM, (2008)