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Disambiguation of "Leibowitz, Brian S."

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A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm.

, , , , , , and . IEEE J. Solid State Circuits, 48 (11): 2693-2704 (2013)

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Owsej Leibowitz

Yeshayahu Leibowitz

Rolf-Walter Briant

Benoît Briand

Grete Leibowitz

 

Other publications of authors with the same name

A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm., , , , , , and . IEEE J. Solid State Circuits, 48 (11): 2693-2704 (2013)A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on., , , , , and . CICC, page 1-4. IEEE, (2012)A 256-element CMOS imaging receiver for free-space optical communication., , and . CICC, page 303-306. IEEE, (2004)Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric., , , , , , , , , and . IEEE J. Solid State Circuits, 43 (9): 2144-2156 (2008)Integration of vision, force and tactile sensing for grasping, , , and . Int. J. Intelligent Machines, (1999)Using tactile and visual sensing with a robotic hand., , , and . ICRA, page 676-681. IEEE, (1997)A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 45 (4): 889-898 (2010)A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface., , , , , , , , , and 10 other author(s). IEEE J. Solid State Circuits, 44 (4): 1235-1247 (2009)A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 50 (4): 814-827 (2015)A 40-Gb/s serial link transceiver in 28-nm CMOS technology., , , , , , , , , and 4 other author(s). VLSIC, page 1-2. IEEE, (2014)