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Disambiguation of "Chen, E-Hung"

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A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm.

, , , , , , and . IEEE J. Solid State Circuits, 48 (11): 2693-2704 (2013)

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Yu-Chen Hung

Hung-Kwan Chen

Chen-Far Hung

Chih-Hung Chen

Hung-Liang Chen

 

Other publications of authors with the same name

Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric., , , , , , , , , and . IEEE J. Solid State Circuits, 43 (9): 2144-2156 (2008)ADC-Based Serial I/O Receivers., and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (9): 2248-2258 (2010)Power Optimized ADC-Based Serial Link Receiver., , and . IEEE J. Solid State Circuits, 47 (4): 938-951 (2012)Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (9): 2096-2107 (2011)A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 50 (4): 814-827 (2015)Edge and Data Adaptive Equalization of Serial-Link Transceivers., , and . IEEE J. Solid State Circuits, 43 (9): 2157-2169 (2008)A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding., , , , , and . VLSIC, page 108-109. IEEE, (2012)A 40-Gb/s serial link transceiver in 28-nm CMOS technology., , , , , , , , , and 4 other author(s). VLSIC, page 1-2. IEEE, (2014)A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering., , , , , , , , , and 4 other author(s). VLSIC, page 1-2. IEEE, (2014)A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm., , , , , , and . IEEE J. Solid State Circuits, 48 (11): 2693-2704 (2013)