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Disambiguation of "Pionteck, Thilo"

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Design of a reconfigurable AES encryption/decryption engine for mobile terminals.

, , , , and . ISCAS (2), page 545-548. IEEE, (2004)

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Thilo Pionteck

Jürgen Pionteck

Hans Thilow

Heinz Thilo

Detlev Thilo-Körner

 

Other publications of authors with the same name

Integration dynamisch rekonfigurierbarer Funktionseinheiten in Prozessoren., , , , and . ARCS Workshops, volume P-41 of LNI, page 155-164. GI, (2004)Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators., , , , , , and . ISQED, page 60-66. IEEE, (2021)Adaptive allocation of default router paths in Network-on-Chips for latency reduction., , and . HPCS, page 140-147. IEEE, (2016)A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip., , , , and . ReCoSoC, page 1-8. IEEE, (2016)A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling., and . ISSoC, page 1-6. IEEE, (2014)Continuous live-tracing as debugging approach on FPGAs., , , and . ReConFig, page 1-8. IEEE, (2017)Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs., , , , , and . CoRR, (2019)Teaching Informatics Students the Secrets of Hardware Design.. MSE, page 31-32. IEEE Computer Society, (2007)Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels., , , , and . PATMOS, page 222-228. IEEE, (2018)Design of a reconfigurable AES encryption/decryption engine for mobile terminals., , , , and . ISCAS (2), page 545-548. IEEE, (2004)