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Towards Designing a Secure RISC-V System-on-Chip: ITUS., , , , , , и . J. Hardw. Syst. Secur., 4 (4): 329-342 (2020)Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks., , , , и . DATE, стр. 561-564. IEEE, (2021)FPGA-based implementation of M4RM for matrix multiplication over GF(2)., , и . VDAT, стр. 1-2. IEEE, (2014)Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems., , , и . VLSI-DAT, стр. 1-4. IEEE, (2014)A Novel Duplication Based Countermeasure to Statistical Ineffective Fault Analysis., , , , , и . ACISP, том 12248 из Lecture Notes in Computer Science, стр. 525-542. Springer, (2020)Recruiting Fault Tolerance Techniques for Microprocessor Security., , , , , и . ATS, стр. 80-85. IEEE, (2019)Secure Your SoC: Building System-an-Chip Designs for Security., , , , , , и . SoCC, стр. 248-253. IEEE, (2020)Lightweight Forth Programmable NoCs., , , и . VLSID, стр. 368-373. IEEE Computer Society, (2018)Relaxation Based Circuit Simulation Acceleration over CPU-FPGA., , , , , и . VLSID, стр. 409-414. IEEE Computer Society, (2016)Parallel two step random walk algorithm to analyze VLSI power grid networks., , , , и . VDAT, стр. 1-2. IEEE Computer Society, (2015)